UCSB Arch Lab / Sept 2024 – Jun 2025

Decompiling Higher-Order Functions in Digital Circuits

ERSP research using PyRTL and Egglog to recover fold abstractions from synthesized netlists and verify Boolean simplifications.

resume
timelineSep 2024 - Jun 2025
focusresearch, systems
stack
  • Python
  • Boolean Logic
  • PyRTL
  • Egglog

problem

Recover higher-order structure (reducers, accumulators, trees) from low-level, synthesized netlists.

approach

Model netlists in PyRTL, translate their structural relationships into Egglog, and apply fold-detection and Boolean-algebra rewrite rules to classify modules and verify simplifications.

implementation notes

  • Conducted research through the Early Research Scholars Program (ERSP) under Prof. Jonathan Balkind on decompiling higher-order functions in digital circuits.
  • Developed methods using PyRTL to model synthesized netlists and leveraged Egglog/e-graphs for fold pattern detection, recovering higher-order abstractions (reducers, accumulators, tree structures) lost during hardware synthesis.
  • Designed and implemented a recursive fold pattern detection algorithm and verified Boolean simplifications via an integrated PyRTL–Egglog workflow.
  • Achieved 88% size reduction in the Add Fold optimization (34→4 modules), demonstrating the effectiveness of the approach.
  • Outcomes: 88% size reduction — Add Fold (34→4); recursive fold-pattern detection; verified simplifications with PyRTL + Egglog.

impact

  • Reduced the Add Fold verification design from 34 modules to 4
  • Detected AND, add, and mux folds in standard designs
  • Presented the methodology and results through UCSB's Early Research Scholars Program
add fold size reduction
88%
modules before
34
modules after
4

links